Image sensors comprise an array of unit elements, called pixels. The array of pixels is exposed to radiation during an exposure period and, subsequently, the signal value of each pixel is read from the array.
Pixel signals are analog signals. An analog-to-digital converter (ADC) is provided to convert the analog pixel signal into a digital signal. The ADCs are a major building block in image sensors and are often the bottleneck in the readout block of the imagers in terms of frame rate, dynamic range and power consumption. Various arrangements have been proposed where analog-to-digital conversion is performed, in parallel, for analog signal values read from columns of the array. This helps to increase the speed at which the pixel array can be read. FIG. 1 shows an example of an image sensor architecture with a pixel array 10 and ADCs 20 provided for each column of the pixel array 10.
One known type of ADC in image sensors is a ramp ADC. This is shown in FIGS. 1 and 2. A ramp generator 21 generates a ramp signal, Vramp, which is distributed to the ADCs 20. Each ramp ADC 20 has a comparator 23 which compares an analog pixel signal ADC_IN[0], . . . ADC_IN[N] received from the pixel array 10 with the ramp signal, Vramp. Each analog-to-digital converter 20 also comprises a counter 24 which is enabled for a period of time based on the comparator output. This time period can be translated to a digital number by the digital counter 24 which is active during this period. Given its mostly digital nature, the ramp ADC scales well with the technology.
FIG. 3 shows the effect of ramp steepness and clock speed on the performance of the ramp converter. The counter value DN corresponds to the digital representation of the input analog signal. One way of reducing the quantisation error, and hence the Least Significant Bit (LSB) value, is to increase the clock speed, as shown in FIG. 3(B). Another way of reducing the quantisation error, and hence the Least Significant Bit (LSB) value, is to reduce the steepness of the ramp, as shown in FIG. 3(C). A significant drawback of reducing the steepness of the ramp is that the input range of the ADC is reduced accordingly. Therefore, the ADC is unable to convert the same range of analog signal values as the ADC of FIG. 3(A).
As each clock cycle corresponds to a quantisation step (LSB), the number of clock cycles needed for N bit resolution is equal to 2N. For example, a 12-bit resolution requires 4096 clock cycles. Even when a high clock speed of 1 GHz is used, it takes over 4 μs time to complete the analog-to-digital conversion. It follows that this converter topology becomes slow and power-inefficient as the number of bits of resolution increases.
Therefore, new solutions are needed to increase the conversion speed of such converter at higher bit resolutions.
To reduce the conversion time and/or reduce the power consumption of the ADCs, a photon-transfer-curve (PTC) method has been proposed for image sensor ADCs. An example is described in the paper “PTC-Based Sigma-Delta ADCs for High-Speed, Low-Noise Imagers”, Xhakoni, A., Ha Le-Thai, T. Geurts, G. Chapinal, and G. Gielen, 2014, Sensors Journal, IEEE 2932-2933. The principle is shown in FIG. 4. In FIG. 4, line A illustrates a signal, line B a photon shot noise and line C a quantization noise.
A PTC-based ADC uses a small quantisation step at low light and a large quantisation step at higher light levels. At high light levels the noise of the readout chain is dominated by the photon shot noise of the photodiode, which is signal dependent. Therefore, the larger quantisation step of the PTC ADC at high light levels has a minimal impact on the SNR. In a ramp ADC, the PTC-based quantisation can be achieved by using two different ramps of different steepness. For example, at high light a ramp with steepness X could be used. At low light a ramp with steepness X/8 would reduce the quantisation step by 8× as well. In case 12-bit low light equivalent resolution is needed, one could use a ramp ADC with the equivalent number of clock cycles of a 9 bit ADC and have a slow ramp with steepness 8× lower than that of the fast ramp, achieving the quantisation step of a 12 bit ADC (LSB12=LSB9/8).
FIG. 5 shows the impact of the PTC-based quantisation in the SNR of the pixel readout chain when a pixel with 10ke-full well is used. The difference in SNR between the PTC-based 12 bit ADC and the conventional 12 bit ADC is a SNR dip of about 0.2 dB at mid-light level.
A few methods have been developed to achieve the PTC-based quantisation step in ramp ADCs. Examples are described in the paper “Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors”, Martijn F. Snoeij, Albert J. P. Theuwissen, Kofi A. A. Makinwa, Johan H. Huij sing, 2007, IEEE JOURNAL OF SOLID-STATE CIRCUITS 2968-2977 and in US 2013/0206961 A1. Snoeij describes a Multiple-Ramp Single-Slope (MRSS) method and a Multiple-Ramp Multiple-Slope (MRMS) method. Both methods require a coarse comparison phase before a fine comparison phase.
The method described in US 2013/0206961 A1 uses a comparator to detect whether the analog signal to be converted is below, or above, a reference level. Depending on the outcome of the comparison, a fast ramp or a slow ramp is used in the ADC to convert the analog signal. This requires a ramp preselection comparator with strict offset requirements. In addition, the conversion time is increased as the ramp preselection is performed before the actual conversion.
The present patent application seeks to provide an alternative analog-to-digital converter.